1. Field of the Invention
The present invention relates to a method for fabricating a semiconductor device; and, more particularly, to a method for fabricating a semiconductor device using a step gated asymmetric recess (STAR) process.
2. Description of the Related Art
Recently, a refresh characteristic has been deteriorated due to short channels formed during a sub-100 nm level dynamic random access memory (DRAM) fabrication. To overcome this limitation, a step gated asymmetric recess (STAR) technology has been introduced. The STAR technology refers to recessing a portion of an active region to several tens of nanometers and having a portion of a gate extending over the recess.
FIGS. 1A to 1D are cross-sectional views illustrating a conventional method for fabricating a semiconductor device using a STAR process. FIGS. 1A and 1C show a substrate structure with a low effective field oxide height (EFH), and FIGS. 1B and 1D show a substrate structure with a high EFH.
As shown in FIGS. 1A and 1B, device isolation regions 12 are formed in predetermined portions of a substrate 11 using a shallow trench isolation (STI) process.
Subsequently, an organic bottom anti-reflective coating layer 13 is formed over the substrate 11 and the device isolation regions 12. Although not illustrated, a photoresist layer is formed over the organic bottom anti-reflective coating layer 13. Then, an exposure and developing process is performed to pattern the photoresist layer to form a STAR mask 14. Portions of the organic bottom anti-reflective coating layer 13 are etched using the STAR mask 14 as an etch barrier.
As shown in FIGS. 1C and 1D, predetermined portions of the substrate 11 are etched to form recessed active regions 15A and 15B.
In the above conventional technology, the organic bottom anti-reflective coating layer 13 is introduced for the easier patterning process of the STAR mask 14; the recessed active regions 15A and 15B are formed; and test patterns 15C and 15D for measuring depths of the recessed active regions 15A and 15B are formed in a peripheral circuit region. That is, because measuring the depths of the recessed active regions 15A and 15B in a cell region is often difficult, the test patterns 15C and 15D are formed in the peripheral circuit region to monitor the depths of STAR patterns, which are the recessed active regions 15A and 15B.
However, in the conventional technology, if a difference in the EFH between the substrate 11 and the individual device isolation region 12 is generated, the organic bottom anti-reflective coating layer 13 is etched with a different thickness. Consequently, the depths of the recessed active regions 15A and 15B become different. That is, the depth STAR1 of the recessed active region 15A with the low EFH (or EFH1) is formed deeper than the depth STAR2 of the recess active region 15B with the high EFH (or EFH2). If an etch target ‘T’ of 400 Å is etched during the recessed active region formation, the maximum depth difference between the recessed active regions 15A and 15B is observed to be 103 Å with respect to the difference of EFH within a wafer. Thus, the depths of the recessed active regions change due to the EFH changes.
For example, if the difference of EFH is 100 Å, the difference of EFH is 100 Å from a wafer to a wafer and from a lot to a lot. Thus, it may be difficult to obtain depth uniformity of the recessed active regions.
Consequently, the depth uniformity defect of the recessed active regions may generate a difference in silicon etch loss, and thus, increases fluctuations with respect to refresh, resistance, and cell threshold voltage within the wafer. That is, the depth uniformity of the recessed active regions may not be obtained due to the difference in EFH between the active regions and the device isolation regions.